A 12-B, 10-MHZ, 250-MW CMOS A D CONVERTER

A 12-b, 10-MHz, 250-mW, four-stage analog-to-digital converter (ADC) w as implemented using a 0.8-mu m p-well CMOS technology, The ADC based on a digitally calibrated multiplying digital-to-analog converter (MDA C) selectively employs a binary-weighted capacitor array in the front- end stage and a unit-capacitor array in the remaining back-end stages to obtain 12 b level linearity while maintaining high yield, All the a nalog and digital circuit functional blocks are fully integrated on a single chip, which occupies a die area of 15 mm(2) (4,2 mm x 3.6 mm), Measured differential nonlinearity (DNL) and integral nonlinearity (IN L) of the prototype are less than +/-0.8 LSE and +/-1.8 LSB, respectiv ely.