LOGIC SYNTHESIS AND OPTIMIZATION ALGORITHM OF MULTIPLE-VALUED LOGIC FUNCTIONS

This paper presents a novel and successful logic synthesis method for optimizing ternary logic functions of any given number of input variab les. A new optimization algorithm to synthesize and minimize an arbitr ary ternary logic function of n-input variables can always lead this f unction to optimal or very close to optimal solution, where [n(n + 1)/ 2]-1 searches are necessary to achieve the optimal solution. Therefore , the complexity number of this algorithm has been greatly reduced fro m O(3n) into O(n2). The advantages of this synthesis and optimization algorithm are: (1) Very easy logic synthesis method. (2) Algorithm com plexity is O(n2). (3) Optimal solution can be obtained in very short t ime. (4) The method can solve the interconnection problems (interconne ction delay) of VLSI and ULSI processors, where very fast and parallel operations can be achieved. A transformation method between operation al and polynomial domains of ternary logic functions of n-input variab les is also discussed. This transformation method is very effective an d simple. Design of the circuits of GF(3) operators, addition and mult iplication mod-3, have been proposed, where these circuits are compose d of Josephson junction devices. The simulation results of these circu its and examples show the following advantages: very good performances , very low power consumption, and ultra high speed switching operation .