AN EXPERIMENTAL 256-MB DRAM WITH BOOSTED SENSE-GROUND SCHEME

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconduct or device with the largest production volume in the 256-Mb era, we mus t develop a cost effective device with a small chip size and a large p rocess tolerance. In this paper, we propose the BSG (Boosted Sense-Gro und) scheme for data retention and FOGOS (FOlded Global and Open Segme nt bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip s ize of 304 mm(2) and a performance of 34 ns access time.