A QUICK INTELLIGENT PAGE-PROGRAMMING ARCHITECTURE AND A SHIELDED BITLINE SENSING METHOD FOR 3-V-ONLY NAND FLASH MEMORY

This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V -only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline- bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure, A 3 V-only experimental NAND flas h memory, developed in a 0.7-mu m NAND flash memory process technology , demonstrates that the programmed threshold voltages are controlled b etween 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-mu s random access time with a 2.7-V po wer supply. The page-programming is completed after the 40-mu s progra m and 2.8-mu s verify read cycle is iterated 4 times. The block-erasin g time is 10 ms.