EFFECT OF PLASMA-ETCHING EDGE-TYPE EXPOSURES ON SI SUBSTRATES - A CORRELATION BETWEEN CARRIER LIFETIME AND ETCH-INDUCED DEFECT STATES

Recently there has been increasing evidence that poly-Si gate reactive ion etching produces gate SiO2 edge damage in MOS transistors in addi tion to the well-known areal plasma charging stress damage. This edge damage is believed to be due to direct exposure of these regions to pl asma photon and particle fluxes. To explore this edge type damage furt her, the effect of this direct exposure on Si substrate is studied usi ng blanket SiO2/Si structures subjected to poly-Si overetches. These s tructures were then characterized using capacitance-voltage and deep l evel transient spectroscopy measurements. Defect states are found in t he Si substrate and at the SiO2/Si interface after this type of overet ch exposure. Their presence is shown to correlate with the degradation of the minority carrier generation lifetime and surface generation ve locity observed by Zerbst measurements.