C. Ramachandran et Fj. Kurdahi, COMBINED TOPOLOGICAL AND FUNCTIONALITY-BASED DELAY ESTIMATION USING ALAYOUT-DRIVEN APPROACH FOR HIGH-LEVEL APPLICATIONS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(12), 1994, pp. 1450-1460
We discuss the problem of accurate delay estimation of cell-based desi
gns, prior to any physical design tasks. For this purpose, we require
accurate wire-length estimates, since wire delays contribute significa
ntly to the overall delay. We present a new technique for wire-length
estimation based on a combination of analytical and constructive appro
aches. Given these wire-length estimates and the cell delays, it is po
ssible to provide worst case delay paths in the design based on the ci
rcuit topology. We have also extended our technique to consider false
paths, which provides more a accurate functionality based estimate tha
t takes into account the estimated layout information. We validate our
technique using the standard MCNC benchmarks. Our results indicate an
average 7% accuracy in the worst case delay predictions for designs w
ith up to about 2800 cells.