DESIGN AND ANALYSIS OF SEGMENTED ROUTING CHANNELS FOR ROW-BASED FPGAS

FPGA's combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic IC 's. The Actel family of FPGA's exemplifies the row-based FPGA model. R ows of logic cells interspersed with routing channels have given this family of FPGA devices the flavor of traditional channeled gate arrays or standard cells. However, unlike the conventional standard cell des ign, the FPGA routing channels contain predefined wiring segments of v arious lengths that are interconnected using antifuses. This paper dev elops analytical models that permit the design of FPGA channel archite cture and the analysis of the routability of row-based FPGA devices ba sed on a generic characterization of the row-based FPGA routing algori thms. In particular, it demonstrates that using probabilistic models f or the origination point and length of connections, an FPGA with prope rly designed segment length and distribution can be nearly as efficien t as a mask-programmable channel (in terms of the number of required t racks). Experimental results corroborate this prediction. This paper d oes not address specifics of the routing algorithms, but investigates the design of the channel segmentation architecture (i.e, various leng ths and patterns of segments and connections among these segments) in order to increase the probability of successful routing.