RESIST - A RECURSIVE TEST PATTERN GENERATION ALGORITHM FOR PATH DELAYFAULTS CONSIDERING VARIOUS TEST CLASSES

This paper presents RESIST, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. Five te st classes are introduced and their properties are discussed. We prese nt an algorithm for deriving a logic system for TPG that results in an earlier recognition of conflicting value assignments. RESIST uses the logic system derived for each test class for an optimal search strate gy. In contrast to other approaches, it exploits the fact that many pa ths in a circuit have common subpaths. RESIST sensitizes those subpath s only once, reducing the number of value assignments during path sens itization signficantly. In addition, our procedure identifies large se ts of untestable path delay faults without enumerating them. RESIST is capable of performing TPG for all path delay faults in all ISCAS-85 a nd ISCAS-89 circuits. For the first time, results for all path delay f aults in circuit c6288 are presented. A comparison with other TPG syst ems revealed that RESIST is significantly faster than all previously p ublished methods.