INTERLEAVED PARALLEL SCHEMES

Authors
SEZNEC A LENFANT J
Citation
A. Seznec et J. Lenfant, INTERLEAVED PARALLEL SCHEMES, IEEE transactions on parallel and distributed systems, 5(12), 1994, pp. 1329-1334
Citations number
8
Categorie Soggetti
System Science","Engineering, Eletrical & Electronic","Computer Science Theory & Methods
Journal title
IEEE transactions on parallel and distributed systems → ACNP
ISSN journal
10459219
Volume
5
Issue
12
Year of publication
1994
Pages
1329 - 1334
Database
ISI
SICI code
1045-9219(1994)5:12<1329:IPS>2.0.ZU;2-P
Abstract
On vector supercomputers, vector register processors share a global hi ghly interleaved memory. In order to optimize memory throughput, a sin gle-instruction, multiple-data (SIMD) synchronization mode may be used on vector sections. We present an interleaved parallel scheme (IPS). Using IPS ensures an equitable distribution of elements on a highly in terleaved memory for a wide range of vector strides. Access to memory may be organized in such a way that conflicts are avoided on memory an d on the interconnection network.