SCALING, OPTIMIZATION AND DESIGN CONSIDERATIONS OF ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS IN CMOS TECHNOLOGY

The effect of scaling on electrostatic discharge (ESD) robustness in 1 .2 to 0.25 mu m channel length CMOS technologies is explored for ESD p rotection circuits and MOSFET structures. Results show that ESD robust ness decreases as ESD structures are scaled to smaller dimensions in f uture technologies. Technology benchmarking, using a standardized ESD design, for evaluating ESD robustness is discussed. The ESD sensitivit y of ESD designs to geometrical and semiconductor process parameters a re evaluated. An analytical development for electro-thermal failure is developed based on electro quasi-static and adiabatic assumptions. ES D scaling relationships are developed applying MOSFET constant electri c field scaling theory. ESD robustness scales as 1/alpha(3/2), where a lpha is the scaling parameter. The scaling relationship derived from t he analytical model is then compared to established power-to-failure E SD models. The impact of MOSFET scaling on the ESD robustness of MOSFE T structures is then discussed. MOSFET scaling as a function of techno logy generation shows that snapback breakover and sustaining voltages are decreasing with each technology generation. Optimization, design c onstraints and technology tradeoffs in CMOS technology development are then shown using a design curve methodology.