DRAMATIC INCREASES IN LATCHUP HOLDING VOLTAGE FOR SUB-0.5 MU-M CMOS USING SHALLOW S D JUNCTIONS/

Large increases in the latchup holding voltage are demonstrated with t he use of shallow source-drain junctions in a sub-0.5 mum CMOS process . Holding voltages well above the supply voltage for 2 mum n+/p+ spaci ngs are demonstrated without the use of complex processes such as retr ograde wells or buried layers. SIMS data is presented to verify the re duction in junction depths to 0.15 mum for the p+/n-well and 0.14 mum for the n+/p-well junction. The improvement in holding voltage is attr ibuted to reductions in parasitic bipolar transistor gains, due to the increase in base width. Well behaved transistor characteristics are p resented using the shallow junction technology.