EXPERIMENTAL EVALUATION OF DYNAMIC SCHEDULING FOR PARALLEL LOGIC SIMULATION USING BENCHMARK CIRCUITS

We discuss a processor scheduling problem for parallel logic simulatio n of combinational circuits. In the processor scheduling problem, to b e discussed in this paper, for logic simulation using time-first metho d, the time needed for each gate evaluation is not given beforehand, a nd is not constant. This feature distinguishes the processor schedulin g problem from typical task scheduling problems. First, we devise newl y Algorithm MET to solve the processor scheduling problem. The key ide a of Algorithm MET is to determine processor scheduling incrementally and dynamically. Then, experimental evaluations using well-known twelv e benchmark combinational circuits show the usefulness of Algorithm ME T, compared with conventional static algorithms. We believe that this is a first step to implement parallel logic simulation of combinationa l circuits.