BIT-SERIAL VLSI SORTER WITH HIGH-RELIABILITY SPECIFICATIONS

This paper presents the design, operation and fault-tolerance enhancem ents of a parallel VLSI sorting architecture for bit-serial input whic h operates as a single pipelined comparator module. The basis design i s enriched with a novel multiple redundancy fault-tolerance scheme so that the sorter meets high reliability specifications. Fault managemen t operates locally at the most basic level of functionality. Hierarchi cal reconfiguration is supported by the fact that only data (no contro l) signals flow throughout the system. Reconfiguration is in real-time and automatic. The proposed sorter is a completely modular system hav ing three levels of modularity, all exhibiting high regularity through out. The sorting time is completely overlapped with the i/o time makin g the overall sorting process very fast. The sorter can sort N numbers of any length k without any modification.