A BICMOS PROGRAMMABLE FREQUENCY-DIVIDER

This paper describes a BiCMOS programmable frequency divider, which is a major functional block of a frequency synthesis IC based on a phase -locked loop. Innovative techniques are demonstrated to solve many inc ompatibility problems between ECL and CMOS techniques. It shows that a similar concept can be applied to other high-speed designs. The frequ ency divider has 15 stages and operates at 165 MHz. It occupies 0.375 mm2 of die area, which is only a third of what is required in a all bi polar version. Power consumption is about 55 mW, which is 80% of that of the all-bipolar version.