A SELF-ALIGNED POCKET IMPLANTATION (SPI) TECHNOLOGY FOR 0.2-MU-M DUAL-GATE CMOS

A novel self-aligned pocket implantation (SPI) technology has been dev eloped. This technology features a localized "pocket" implantation usi ng a gate electrode and TiSi2 films as self-aligned masks. This proces s provides high punchthrough resistance and high current driving capab ility while suppressing the impurity concentration in the twin well. T he drain junction capacitance is decreased by 30% for N-MOSFET and by 49% for P-MOSFET, compared to conventional LDD devices. It is found th at a dual-gate CMOS fabricated by the SPI technology achieves high cir cuit performance.