HOT-CARRIER DEGRADATION OF SINGLE-DRAIN PMOSFETS WITH DIFFERING SIDEWALL SPACER THICKNESSES

The effect of the sidewall spacer thickness on the hot-carrier degrada tion of buried-channel PMOS transistors with a sidewall-offset single- drain structure was studied. At the bias stress condition of maximum g ate current, a large degradation was observed for transistors with no overlap between gate and drain. Results of measurements using the char ge-pumping technique suggest that trapping of a large number of electr ons in the CVD SiO2 sidewall spacer is responsible for the enhanced de gradation. This was also confirmed by the measurement of the threshold voltage as a function of drain bias.