EVALUATING DESIGN CHOICES FOR SHARED BUS MULTIPROCESSORS IN A THROUGHPUT-ORIENTED ENVIRONMENT

This paper considers the evaluation of design choices in multiprocesso rs with a single, shared bus interconnect operating in a throughput-or iented, multiprogrammed environment, that is, an environment in which each task is being executed on a single processor and the performance of the multiprocessor is measured by its overall throughput. To evalua te design choices, we develop mean value analysis analytical models an d validate our models by comparing their results against the results o f a trace-driven simulation analysis for 5376 multiprocessor configura tions. The trace-driven simulation uses actual programs and simulates their execution in a throughput-oriented environment. Using multiproce ssor throughput as a performance metric and the mean value analysis mo dels as tools, we evaluate several design choices. We find that: 1) ca che block sizes that yield the best performance in a multiprocessor di ffer from the block sizes that yield the best uniprocessor performance metrics, 2) a larger cache set associativity might be warranted in a multiprocessor even though it might not be warranted in a uniprocessor , 3) a split transaction, pipelined bus yields much higher multiproces sor throughput than a circuit switched bus, especially for larger main memory latencies, and 4) increasing the bus width appears to be an ef fective way of improving multiprocessor throughput.