A FULLY INTEGRATED 6.25-PERCENT PULL-IN RANGE DIGITAL PLL FOR ISDN PRIMARY RATE INTERFACE LSI

A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS o scillator is described. Nominal division number of the variable divide r is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may in crease if the pull-in range is widened. To overcome this problem, outp ut jitter is reduced by utilizing the dual loop architecture. Wide pul l-in range enables us to use on-chip oscillator, which is not so preci se as the expensive crystal oscillator. This CMOS oscillator must be c arefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. C ircuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.