EFFECT OF SIDEWALL SPACER THICKNESS ON HOT-CARRIER DEGRADATION OF PMOS TRANSISTORS

The effect of the sidewall spacer thickness on the hot-carrier degrada tion of sidewall-offset single drain PMOS transistors was studied. At the stress bias condition of maximum gate current, a large degradation was observed when there is no overlap between gate and drain. The tra pping of a large number of electrons in the sidewall oxide spacer is a ttributed to this. In the off-state, PMOS transistors were degraded by electrons generated by the band-to-band tunnelling process. Transisto rs with no gate-to-drain overlap show little degradation at relatively low V(d), because of the small drain leakage current by band-to-band tunnelling. However, as V(d) is increased and the drain leakage curren t reaches a certain level, the degree of degradation drastically incre ases. As in the case of the DC stress test at the peak gate current, t his is probably a result of enhanced trapping of injected electrons in the sidewall spacer. These results suggest that there should be an ov erlap between gate and drain but that the overlap distance should be k ept to a minimum in order to maximize the hot-carrier resistance of PM OSFETs. The single drain PMOS transistor with the optimum sidewall spa cer thickness has a lifetime which is much longer than 10 years at an operation voltage of -3.3V.