DIGITAL SYSTEM-DESIGN IN THE PRESENCE OF SINGLE EVENT UPSETS

We consider the effects of single event upsets (SEU) on digital system s, and show techniques for designing reliable systems with current lev els of SEU protection. We consider three main systems: main memory, lo gic, and cache memory. We also describe a design of main and cache mem ory subsystems which are SEU protected. We consider three main subsyst ems: main memory, logic, and cache memory. With SEU defined in bit day s p, and using single error correction we show that for all subsystems considered we can obtain an effective upset rate which is proportiona l to the product of p2 and the time between corrections, or scrub time . In particular, we have used data for memory chip size and performanc e derived from the Gallium Arsenide (GaAs) pilot lines funded by the D efense Advanced Research Projects Agency (DARPA) throughout the 1980s.