A 500-MEGABYTE S DATA-RATE 4.5M DRAM

Authors
KUSHIYAMA N OHSHIMA S STARK D NOJI H SAKURAI K TAKASE S FURUYAMA T BARTH RM CHAN A DILLON J GASBARRO JA GRIFFIN MM HOROWITZ M LEE TH LEE V
Citation
N. Kushiyama et al., A 500-MEGABYTE S DATA-RATE 4.5M DRAM, IEEE journal of solid-state circuits, 28(4), 1993, pp. 490-498
Citations number
2
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
28
Issue
4
Year of publication
1993
Pages
490 - 498
Database
ISI
SICI code
0018-9200(1993)28:4<490:A5SD4D>2.0.ZU;2-3
Abstract
In order to improve system bus bandwidth, a novel, small-swing, synchr onous bus, which is based on a block-transfer-oriented protocol, has b een proposed. A 4.SM DRAM that interfaces to the bus directly and prov ides a 500-megabyte/s data rate has been developed.