A CURRENT-CONTROLLED LATCH SENSE AMPLIFIER AND A STATIC POWER-SAVING INPUT BUFFER FOR LOW-POWER ARCHITECTURE

Authors
KOBAYASHI T NOGAMI K SHIROTORI T FUJIMOTO Y
Citation
T. Kobayashi et al., A CURRENT-CONTROLLED LATCH SENSE AMPLIFIER AND A STATIC POWER-SAVING INPUT BUFFER FOR LOW-POWER ARCHITECTURE, IEEE journal of solid-state circuits, 28(4), 1993, pp. 523-527
Citations number
7
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
28
Issue
4
Year of publication
1993
Pages
523 - 527
Database
ISI
SICI code
0018-9200(1993)28:4<523:ACLSAA>2.0.ZU;2-1
Abstract
This paper describes two new power-saving schemes for high-performance VLSI's with a large-scale memory and many interface signals. One is a current-controlled latch sense amplifier that reduces the power dissi pation by stopping sense current automatically. This sense amplifier r educes power without degrading access time compared with the conventio nal current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces dc current in interface circuits re ceiving TTL-high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM.