A CAPACITOR OVER BIT-LINE (COB) STACKED CAPACITOR CELL USING LOCAL INTERCONNECT LAYER FOR 64 MBDRAMS

A new capacitor over bit-line (COB) stacked capacitor memory cell was developed using a local interconnect poly-silicon layer to arrange a c apacitor contact between bit-lines. This memory cell enables usable ca pacitor area to increase and capacitor contact hole depth to decrease. The hemispherical grain (HSG) silicon, whose effective surface area i s twice that of ordinary poly-silicon, was utilized for the storage no de to increase the storage capacitance without increasing the storage node height. The feasibility of achieving a 1.8 mum2 memory cell with 30 fF storage capacitance using a 7 nm-SiO2-equivalent dielectric film and a 0.5 mum-high HSG storage node has been verified for 64 MbDRAMs by a test memory device using a 0.4 mum CMOS process.