FAILURE ANALYSIS OF HIGH-DENSITY CMOS SRAMS - USING REALISTIC DEFECT MODELING AND IDDQ TESTING

Authors
NAIK S AGRICOLA F MALY W
Citation
S. Naik et al., FAILURE ANALYSIS OF HIGH-DENSITY CMOS SRAMS - USING REALISTIC DEFECT MODELING AND IDDQ TESTING, IEEE design & test of computers, 10(2), 1993, pp. 13-23
Citations number
15
Categorie Soggetti
Computer Sciences","Computer Applications & Cybernetics
Journal title
IEEE design & test of computers → ACNP
ISSN journal
07407475
Volume
10
Issue
2
Year of publication
1993
Pages
13 - 23
Database
ISI
SICI code
0740-7475(1993)10:2<13:FAOHCS>2.0.ZU;2-S
Abstract
The authors have developed a rapid failure analysis method for high-de nsity CMOS SRAMs, using realistic defect modeling and results of funct ional and I(DDQ) testing. Key to the method is the development of a de fect-to-signature vocabulary through inductive fault analysis. Results indicate that the method can efficiently debug the multimegabit-memor y manufacturing process.