A SYSTOLIC REDUNDANT RESIDUE ARITHMETIC ERROR CORRECTION CIRCUIT

In highly integrated processors, a concurrent fault tolerance capabili ty is particularly important especially for real-time applications. In fact, in these systems, transient errors are often present, but can h ardly be corrected on line. Error recovery procedures applied on each processing or memory element require large amount of hardware and can reduce throughput. The residue number arithmetic has intrinsic fault t olerance capability and can allow hardware complexity reduction. The e rror detection and correction by residue number arithmetic was approac hed by several authors in the technical literature. In this paper we p ropose a single error correction procedure based on the use of redunda nt residue number system (RRNS) and the base extension operation. The proposed method uses a very small decision table and works in parallel mode, therefore it is suitable for high speed VLSI circuit realizatio n. In the paper a parallel systolic architecture which realizes the al gorithm is introduced.