MULTIBIT CORRECTING DATA INTERFACE FOR FAULT-TOLERANT SYSTEMS

Failures of complex integrated circuits in modern computer systems can affect several bits simultaneously, easily overwhelming standard comm ercially available correction or detection subassemblies. A fault-dete cting, bidirectional data interface between uncoded data from one part , such as a processor, and coded data in the rest of the system is des cribed. This interface is capable of correcting a single multibit symb ol error or detecting the occurrence of two such errors. The device us es a shortened Reed-Solomon code and two practical symbol sizes are co nsidered; nibble (4-bit) errors are protected by a (40, 32) binary equ ivalent shortened code while byte errors are covered by a (80, 64) bin ary-sized code. The Reed-Solomon codes have maximum protection levels, even when shortened, and allow simplifying design options. A dual ort hogonal basis used for the symbols' respresentations provides signific ant hardware savings. The interface unit achieves internal fault detec tion, sensing any single subassembly failure, by comparing regenerated parity values in a totally self-checking equality checker. The probab ility of undetected error and memory reliability values are easily cal culated since the weight distributions for shortened Reed-Solomon code s are developed. A fault-tolerent ultra-reliable memory module is prop osed and its reliabilities evaluated. An example design for a nibble-c orrecting interface is realized using a single desktop programmable ga te array and requires a fault detection overhead in module count of ab out 15 %.