STUDY AND IMPROVEMENT OF ANOMALOUS INTERFACE STATES OF METAL-OXIDE-SEMICONDUCTOR STRUCTURES INDUCED BY RAPID THERMAL POST-OXIDE ANNEALING

Anomalous interface states were caused by post-oxide rapid thermal ann ealing in an n+ polycrystalline silicon metal-oxide-semiconductor capa citor. These anomalous interface states have been investigated using h igh/low frequency capacitance/gate voltage (C/V) measurements. An addi tional annealing process (450-degrees-C, 30 min in 90% N2/10% H-2 mixe d gas) was found to improve the anomalous interface states. The improv ed results were identified using a constant current injection stress t est.