POWER PARTITION AND EMITTER SIZE OPTIMIZATION FOR BIPOLAR ECL CIRCUIT

This paper describes an automated approach for optimizing the performa nce of bipolar ECL circuit. A quadratic equation representing an appro ximate surface is used to express the circuit delay in terms of the po wer partition and current densities in the current-switch and the emit ter-follower stages. During the iteration of the optimization process, the optimal obtained from the present approximate surface is used as the new nominal point for the next iteration. As the nominal point con verges to the optimal, the approximate surface converges to a section of the real optimum surface. This methodology transforms the circuit o ptimization into a multivariable optimization problem and is shown to provide an optimum design with circuit analysis accuracy. The design c onsiderations of high-performance ECL circuits are also discussed.