FLOATING CMOS RESISTOR

A floating resistor scheme is described in which a CMOS device is line arised by the application of a suitably scaled common-mode signal to t he gate terminal only. SPICE studies indicate that the proposed resist or offers low distortion over a tuning range of 3:1. The design, for w hich a patent application has been filed, makes no special demands on device aspect ratios and could offer an economic alternative to fully- balanced topologies.