25 GBIT S DECISION CIRCUIT, 34 GBIT/S MULTIPLEXER, AND 40 GBIT/S DEMULTIPLEXER IC IN SELECTIVE EPITAXIAL SI BIPOLAR TECHNOLOGY/

Authors
FELDER A STENGL R HAUENSCHILD J REIN HM MEISTER TF
Citation
A. Felder et al., 25 GBIT S DECISION CIRCUIT, 34 GBIT/S MULTIPLEXER, AND 40 GBIT/S DEMULTIPLEXER IC IN SELECTIVE EPITAXIAL SI BIPOLAR TECHNOLOGY/, Electronics Letters, 29(6), 1993, pp. 525-527
Citations number
6
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
29
Issue
6
Year of publication
1993
Pages
525 - 527
Database
ISI
SICI code
0013-5194(1993)29:6<525:2GSDC3>2.0.ZU;2-9
Abstract
A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0-8 mum lithography. The data rates achieved are the highest values reported for these types of circuit in any IC t echnology.