ADA PARALLELISM APPLIED TO VLSI CIRCUIT SIMULATORS

In this paper, we introduce a new algorithm of parallel timing simulat ion for VLSI circuits. The simulator takes into consideration the conc ept of parallelism, it generates nodes (or generators) tasks according to nodes (or generators) number in the circuit and one relaxation tas k that controls the evolution of the signals in the circuit and trigge rs, if necessary, the iterative loop until convergence. The Ada kernel provides to each task the possibility of parallel execution with the others.