Working jointly at MIT, LSI Logic, and Sun Microsystems, designers cre
ated the sparcle processing chip by evolving an existing RISC architec
ture toward a processor suited for large-scale multiprocessors. This c
hip supports three multiprocessor mechanisms: fast context switching,
fast, user-level message handling, and fine-grain synchronization. The
Sparcle effort demonstrates that RISC architectures coupled with a co
mmunications and memory management unit do not require major architect
ural changes to support multiprocessing efficiently.