EFFICIENT TECHNIQUE FOR GENERATING MINIMUM TEST SETS FOR GENERAL TREELOGIC-CIRCUITS

This paper constructs, in a simple manner, a minimum test set for gene ral tree logic circuits from the test sets of its nodes. A general com binational circuit can in most cases be decomposed to modules such tha t these modules constitute the basic logic elements of a tree circuit. Basically, our technique relies on the characteristics of tree circui ts in which no backtracking is necessary after assigning one or zero t o any signal line in them. The number of tests in the generated test s et has an upper bound of 2n, with n being the number of the primary in puts of the given circuit.