SWITCH-LEVEL TIMING SIMULATION OF BIPOLAR ECL CIRCUITS

Virtually all the reported works in the area of logic and timing simul ation of VLSI circuits have been focused on MOS circuits. Recently, bi polar VLSI has emerged as a viable technology for high gate count digi tal IC's. In this paper we present an approach for switch-level timing simulation of bipolar ECL digital circuits. The approach is based on the development of a switch-level model of the transistor and on the r epresentation of the circuit by a switch-graph. The circuit is partiti oned into subcircuits, and the symbolic logic expressions are then gen erated, which represent the logic states of the nodes in terms of subc ircuit inputs and initial conditions. Timing information is computed u sing a new physical delay model based on device equations, transistor interconnection, input slew rate, and loading conditions. The delay mo del was derived based on the average branch current analysis and incor porates more than 15 delay-sensitive circuit and SPICE BJT model param eters. The use of a novel parametric correction scheme permits greater freedom to handle complex effects such as high-level injection, paras itic resistances and interconnection delay, than would otherwise be po ssible. In addition, the dynamic fanout effects due to base leakage cu rrent are incorporated by a fanout collapsing technique. The switch-le vel graph model and the delay model provides fast, accurate and reliab le timing simulation of ECL circuits. For large circuits, the proposed approach provides delay estimates that are typically within 10% of SP ICE's estimates, with three orders of speed improvement.