TEST-GENERATION TO MINIMIZE ERROR MASKING

Built-in self-test (BIST) schemes provide on-chip circuitry to generat e test vectors and to analyze output responses so that testing can be performed on site without using external testing devices. Usually in B IST schemes test-pattern generation and output compaction are addresse d separately. We present a unified approach to test-pattern generation and output compaction and show that partial control over test-pattern sequence can give zero aliasing in single-output combinational circui ts (by reordering the test set to obtain a periodic output and uniquel y identifying it) and reduced aliasing in multiple-output combinationa l circuits (by reordering the test set to obtain a periodic quotient f rom the multiple-input signature register and uniquely identifying it) , under more practical constraints. Exact aliasing probability for the latter case is also derived for the independent bit error model. Unli ke the schemes that discard the quotient, aliasing probability of the proposed scheme reaches zero for large test lengths. Experimental resu lts obtained for benchmark circuits are provided to show the practicab ility of the approach.