AN ANALOG CMOS CHIP SET FOR NEURAL NETWORKS WITH ARBITRARY TOPOLOGIES

An analog CMOS chip set for implementations of artificial neural netwo rks (ANN's) has been fabricated and tested. The chip set consists of t wo cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synap se chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using ''parasitic '' lateral bipolar transistors. The synapse test chip is a cascadable 4 x 4 matrix-vector multiplier with variable, 10 bit resolution matrix elements. The propagation delay of the test chips was measured to 2.6 mus per layer.