A CMOS ANALOG ADAPTIVE BAM WITH ON-CHIP LEARNING AND WEIGHT REFRESHING

In this paper we will extend the transconductance-mode (T-mode) approa ch [1] to implement analog continuous-time neural network hardware sys tems to include on-chip Hebbian learning and on-chip analog weight sto rage capability. The demonstration vehicle used is a 5+5 neurons bidir ectional associative memory (BAM) prototype fabricated in a standard 2 -mum double-metal double-polysilicon CMOS process (through and thanks to MOSIS). Mismatches and nonidealities in learning neural hardware ar e supposed not to be critical if on-chip learning is available, becaus e they will be implicitly compensated. However, mismatches in the lear ning circuits themselves cannot always be compensated. This mismatch i s specially important if the learning circuits use transistors operati ng in weak inversion. In this paper we will estimate the expected mism atch between learning circuits in the BAM network prototype and evalua te its effect on the learning performance, using theoretical computati ons and Monte Carlo Hspice simulations. Afterwards we will verify thes e theoretical predictions with the experimentally measured results on the test vehicle prototype.