A FAST PIPELINED VLSI ADDER FOR FAST TRIGGER DECISIONS AT THE SUPERCONDUCTING SUPER COLLIDER

We present a four 12-bit binary number adder proposed for use in the c omputation of the pipelined energy sums of data from the detectors at the Superconducting Super Collider (SSC). It was fabricated using a 1. 2 mum N-well CMOS process. It comprises three 12-bit adders organized as a two-stage pipeline. To compute the final carry of each of the 12- bit adders, we used the Carry-Select technique applied to their 4-bit adder subcells. The 4-bit adders used the Carry-Lookahead method to co mpute their carries. In order to reduce the circuit area and to simpli fy the structure of this application specific integrated circuit (ASIC ) we employed a Multiple-Output Domino Logic design style. The first s tage of the pipeline (two adders) performs two 12-bit additions in par allel while the second stage (one adder) finishes up the previously st arted computation. The pipeline is driven using a two-phase clocking s trategy by processing a single-phase external clock. We achieved an wo rst case throughput of 18 ns. In the best case the throughput was 16.5 ns. We included a built-in facility for testing the first stage of th e pipeline. The area of the circuit is 1425 x 5510 mum2, it has 76 pad s, and it is packed in a 132 pin grid array (PGA). The transistor coun t is 6639. The dissipated power at a 18-ns clock period was almost-equ al-to 0.75 W. The circuit has been fabricated through the MOSIS servic e. We found an yield of almost-equal-to 80% for a lot of 50 chips.