AN EXPERIMENTAL-STUDY OF TESTING TECHNIQUES FOR BRIDGING FAULTS IN CMOS ICS

The paper presents an experimental analysis of DFT techniques used to detect the presence of faulty resistive paths throughout CMOS IC's. Cu rrent monitoring, delay fault testing, and new design-for-testability (DFT) techniques are compared by means of a chip designed ad hoc that allows the presence of resistive bridgings within standard functional blocks to be simulated via hardware. The results presented in this wor k suggest that specific DFT techniques offer considerable advantages o ver more conventional approaches.