Electrostatic discharge (ESD) is considered a major reliability threat
to integrated circuit (IC) technologies. A review of the ESD phenomen
a along with the test methods, the appropriate on-chip protection tech
niques, and the impact of process technology advances from CMOS to BiC
MOS on the ESD sensitivity of IC protection circuits, are presented. T
he present status of understanding the ESD failure physics and the cur
rent approaches for modeling are also discussed This overview paper de
als with several aspects of ESD from the point of view of the test, de
sign, product, and reliability engineers.