ARCHITECTURES FOR THE IMPLEMENTATION OF A FIXED DELAY TREE-SEARCH DETECTOR

This paper examines the tradeoff between fixed delay tree search (FDTS ) detector complexity and performance with various modulation codes, S everal architectures suitable for implementing FDTS or achieving perfo rmance comparable to FDTS are presented. Recursive forms are derived b y decomposing the branch metric computation while breaking down the en tire path metric yields nonrecursive forms, The final architecture cas ts the detection problem Into a signal space context in which the obse rvation space is partitioned into decision regions, These structures a re presented and evaluated in the context of an analog very large scal e integration (VLSI) implementation, Compared to a direct mapping to h ardware of the original algorithm, these alternative schemes offer red uced power consumption and/or increased data rate.