A 622-MB S 8X8 ATM SWITCH CHIP SET WITH SHARED MULTIBUFFER ARCHITECTURE/

An asynchronous transfer mode (ATM) switch chip set, which employs a s hared multibuffer architecture, and its control method are described. This new switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crossp oint switch so as to equalize the number of stored ATM cells in each b uffer memory, these buffer memories can be recognized as a single larg e shared buffer memory. Thus, buffers are used efficiently and the cel l loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtu e of parallel access to the buffer memories via the crosspoint switche s. Access time for the buffer memory is thus greatly reduced. This fea ture enables the high-speed switch operation. We developed a three-VLS I chip set using 0.8-mum BiCMOS process technology. Four aligner LSI's , nine bit-sliced buffer-switch LSI's, and one control LSI were combin ed to create a 622-Mb/s 8 x 8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using the time-division multiplexing.