PERFORMANCE OPTIMIZATION OF PIPELINED LOGIC-CIRCUITS USING PERIPHERALRETIMING AND RESYNTHESIS

We consider the problem of minimizing the cycle time of a given pipeli ned circuit. Existing approaches are suboptimal since they do not cons ider the possibility of simultaneously resynthesizing the combinationa l logic and moving the latches using retiming. In [10] the idea of sim ultaneous retiming and resynthesis was introduced. We use the concepts presented there to optimize a pipelined circuit to meet a given cycle time. An instance of the pipelined cycle optimization problem is spec ified by the circuit, a set of input arrival times relative to the clo ck, a set of output required times relative to the clock, and a given cycle time that it must meet. Given the instance of the pipelined perf ormance optimization problem we construct an instance of a combination al speedup problem. This is specified by a combinational logic circuit , a set of arrival times on the inputs, and a set of required times fo r the outputs which must be met. We then give a constructive proof tha t the pipelined problem has a solution if and only if the combinationa l problem has a solution. This result is significant since it shows it is enough to consider only the combinational speedup problem and all known techniques for that (e.g., [12], [13]) can be directly applied t o generate a solution for the pipelined problem.