SEQUENTIAL TEST-GENERATION AND SYNTHESIS FOR TESTABILITY AT THE REGISTER-TRANSFER AND LOGIC LEVELS

The problem of test generation for non-scan sequential VLSI circuits i s addressed. A novel method of test generation that efficiently genera tes test sequences for stuck-at faults in the logic circuit by exploit ing register-transfer-level (RTL) design information is presented. Our approach is targeted at circuits with highly connected State Transiti on Graphs (STG) as in data paths. However, we never explicitly make us e of the STG. The problem of sequential test generation is decomposed into three subproblems of combinational test generation, fault-free st ate justification, and fault-free differentiation. Standard combinatio nal test generation algorithms are used to generate test vectors for s tuck-at faults in the logic-level implementation. The required state c orresponding to the test vector is justified using a fault-free justif ication step that is performed using the RTL specification. Similarly, if the effect of the fault has been propagated by the test vector onl y to the flip-flop inputs, the faulty state produced is differentiated from the true next state by a differentiation step that uses the RTL specification. New and efficient algorithms for fault-free state justi fication and differentiation on RTL descriptions that contain arithmet ic as well as random logic modules are described. Unlike previous appr oaches, this approach does not require the storage of covers or a part ial STG and can be used to generate tests for entire chips without sca n. Exploiting RTL information, together with a new conflict resolution technique, results in improvements of up to 100 X in performance over sequential test generation techniques restricted to operate only at t he logic level. Tests have been generated for the viterbi speech proce ssor chip [31] using this approach. The problem of synthesis of sequen tial logic for testability is also addressed. This involves the automa tic synthesis of nonscan sequential circuits that are completely or hi ghly testable under a fault model. A synthesis for testability approac h is presented that also uses the register-transfer level (RTL) specif ication of a sequential circuit to derive a fully testable implementat ion of the circuit. The focus is on the development of a synthesis str ategy of don't-care exploitation and logic partitioning that results i n a fully testable implementation of the sequential machine. Prelimina ry experimental results indicate that large sequential circuits (e.g., FSM controllers, data paths) with a large number of latches and gates can be synthesized to be fully non-scan testable using these techniqu es.