STEPWISE EQUIVALENT CONDUCTANCE CIRCUIT SIMULATION TECHNIQUE

In this paper we introduce a new circuit simulation technique based on a stepwise equivalent conductance model of a nonlinear resistive devi ce. The major advantage of this technique is to eliminate the need for employing Newton-Raphson iterations for the implicit integration. The technique, when applicable, is consistent, absolutely stable, and con vergent. Furthermore, we demonstrate that a second order of accuracy ( the local truncation error for integration is of the cubic order of th e time step used) is achieved by solving linear equations for each int egration step. When applied to digital MOS circuits, the technique tak es advantage of the fact that voltage waveforms can be modeled to a go od approximation as piecewise-linear functions and thus achieve furthe r speed-up in the simulation. The program, called SWEC, has been imple mented, and has proven to be accurate and efficient on a large number of circuit examples. The comparisons of results with Relax2.3 [7], iSP LICE3.0 [5], [17], XPsim [2], and SPECS2 [31 are given.