ON OPTIMIZING VLSI TESTING FOR PRODUCT QUALITY USING DIE-YIELD PREDICTION

This paper proposes a new adaptive testing procedure that uses spatial defect clustering information, and the available test results for nei ghboring dies to optimize test costs for VLSI testing. For the same av erage test costs, our approach shows the potential for better than a f actor-of-two improvement in average defect levels. Perhaps more signif icantly, it also allows the separation of high-quality circuits with d efect levels more than an order of magnitude better than the average f or the production run. Our proposal is orthogonal to all other approac hes for improving defect levels and can be combined with them.