REALISTIC FAULT MODEL FOR EXTERNAL SHORTS IN MOS TECHNOLOGIES

The Letter focuses on the fault modelling of external shorts in n-, C- and BiC-MOS digital circuits. In the context of functional testing, i t is demonstrated that eight different electrical configurations may a ppear depending on the topological and technological parameters of the fault. Therefore, eight new logical models are defined showing that t he wired-OR and wired-AND models, classically used for test pattern ge neration, fault simulation and defect coverage evaluation are not suff icient.