A TIGHT CLOCK SYNCHRONIZATION TECHNIQUE FOR MULTIPROCESSOR SYSTEMS

In this paper we present a tight clock synchronization scheme for larg e-scale multiprocessor systems. The proposed scheme consists of two sy mmetric loops for transmission of the master clock signals and a skew cancellation circuit (SCC) for each node to be synchronized to the mas ter clock. Each clocking signal generated by the master clock source i s replicated into two identical copies and the twin signals are transm itted on two symmetric loops in opposite directions. To cancel the tim e skew between them caused by the transmission network, the time diffe rence between the two clocks' arrival times at any node is first measu red and stored in each node. Then each of the leading signals received from the loop in a node is issued to its functional units after the s ignal is delayed by half the measured phase difference. It is shown th at the system clock skew can be made independent of the delay of the t ransmission lines by the proposed scheme at a low hardware cost. To ex plore the feasibility of the proposed scheme, the SCC is designed with a combination of programmable delay element arrays and a phase detect or. The floor-plan of the SCC is implemented by the MAGIC VLSI lay-out tool based on MOSIS CMOS 2 mum technology and extensively simulated.