A SHARED MULTIBUFFER ARCHITECTURE FOR HIGH-SPEED ATM SWITCH LSIS

A new shared multibuffer architecture for high-speed ATM (Asynchronous Transfer Mode) switch LSIs is described. Multiple buffer memories are located between two crosspoint switches. By controlling the input-sid e crosspoint switch so as to equalize the utilization rate of each buf fer memory, these multiple buffer memories can be recognized as a sing le large shared buffer memory. High utilization efficiency of buffer m emory can thus be achieved, and the cell loss ratio is minimized. By a ccessing the buffer memories in parallel via crosspoint switches, the time required to access the buffer memories is greatly reduced. This f eature enables high-speed operation of the switch. The shared multibuf fer architecture was implemented in a switch LSI using 0.8-mum BiCMOS process technology. Experimental results revealed that this chip can o perate at more than 125 MHz. Bit-sliced eight switch LSIs operating at 78 MHz construct a 622-Mb/s 8 x 8 ATM switching system with a buffer size of 1,024 ATM cells. Power consumption of the switch LSI was 3 W.