A 12-BIT RESOLUTION 200 KFLIPS FUZZY INFERENCE PROCESSOR

A fuzzy inference processor which performs fuzzy inference with 12-bit resolution input at 200 kFLIPS (Fuzzy Logical Inference Per Second) h as been developed. To keep the cost performance, not parallel processi ng hardware but processor type hardware is employed. Dedicated members hip function generators, rule instructions and modified add/divide alg orithm are adopted to attain the performance. The membership function generators calculate a membership function value in less than a half c lock cycle. Rule instructions calculate the grade of a rule by one ins truction. Antecedent processing and consequent processing are pipeline d by the modified add/divide algorithm. As a result, total inference t ime is significantly reduced. For example, in the case of typical infe rence (about 20 rules with 2 to 4 inputs and 1 output), the total infe rence needs approximately 100 clock cycles. Furthermore by adding a me chanism to calculate the variance and maximum grade of the final membe rship function, it is enabled to evaluate the inference reliability. T he chip, fabricated by 1 mum CMOS technology, contains 86k transistors in a 7.5 x 6.7 mm die size. The chip operates at more than 20 MHz clo ck frequency at 5V.